1. Field of the Invention
The present invention relates to a semiconductor memory device such as a NAND flash memory.
2. Description of the Related Art
In a NAND flash memory, a plurality of cells, which are arranged in a column direction, are connected in series, thereby constituting a NAND unit, and a plurality of NAND units constitute a block. Data write is executed in units of plural memory cells which are connected to a selected word line, and data erase is executed in units of a block.
A write voltage (program voltage) VPGM and an erase voltage VERASE of the NAND flash memory are generated by using a boost circuit which boosts, e.g. a power supply voltage (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 2008-54471). In the NAND flash memory, when data is written in a memory cell which is connected to a word line of a selected block, the program voltage VPGM is transferred to the word line via a driving transistor. One end of the current path of this driving transistor is connected to a control gate driver to which the program voltage VPGM is supplied, and the other end of the current path is connected to the word line. Further, the gate of the driving transistor is connected to a row decoder. By the activation of the row decoder, the driving transistor is turned on, and the program voltage VPGM that is supplied from the control gate driver is transferred to the word line. In addition, in order to transfer the program voltage VPGM, the voltage that is supplied from the row decoder to the gate of the driving transistor is set at VPGMH (=VPGM+Vth) which is higher than the program voltage VPGM by a degree corresponding to a threshold voltage Vth of the driving transistor.
On the other hand, at the time of erase, 0 V is transferred to the word line of the selected block via the driving transistor. Specifically, the gate of the driving transistor is set at the voltage VPGMH, the output voltage of the control gate driver is set at 0 V, and the word line is set at 0 V. In addition, the voltage of a p-type substrate is raised from 0 V to the erase voltage VERASE. Hence, a potential difference of the erase voltage VERASE occurs between the control gate and the substrate, and electrons are extracted from the floating gate to the substrate.
In a non-selected block, since the gate of the driving transistor is set at 0 V and the output voltage of the control gate driver is 0 V, the driving transistor is turned off, and the word line, which is connected to this driving transistor, is set in a floating state. At the time of erase, the voltage of the p-type substrate is boosted from 0 V to the erase voltage VERASE. Consequently, by the capacitive coupling between the substrate and the control gate, the potential of the control gate rises from 0 V to the neighborhood of VERASE. Since no potential difference occurs between the substrate and the control gate, the non-selected block is set in an erase non-selection state.
In the meantime, at the time of erase, in the driving transistor of the non-selected block, the drain (word line) is boosted to the erase voltage VERASE, and the gate and source are set at 0 V. Accordingly, a high electric field is applied between the drain and the gate and between the drain and the source. Thus, if the erase is repeatedly executed, the characteristics of the driving transistor may possibly vary.
On the other hand, even in the case where erase is repeated, the characteristics of a trimming transistor Tr_LIM, which generates a program voltage VPGM from a boost voltage VPGMH, do not vary. Thus, if the threshold voltage of the trimming transistor Tr_LIM is Vth(Tr_LIM), the output voltage V(Tr_LIM) of the trimming transistor Tr_LIM is expressed byV(Tr_LIM)=VPGMH−Vth(Tr_LIM)=VPGM.
For example, in the case where the threshold voltage Vth of the driving transistor rises due to a characteristic change of the driving transistor, if the variation amount of the voltage, which can be transferred to the word line at the time of write, is ΔVth, the transferable voltage VTr is expressed byVTr=VPGMH−(Vth(Tr_LIM)−ΔVth)=VPGM−ΔVth.
As has been described above, in the case where the characteristics of the driving transistor have varied relative to the trimming transistor, it becomes difficult for the driving transistor to transfer the program voltage VPGM to the word line. A voltage, which is lower than the program voltage VPGM by ΔVth, is supplied. Furthermore, since the driving transistor is not fully rendered conductive, the current driving performance of the driving transistor lowers. Therefore, there has been a demand for a semiconductor memory device which can compensate a voltage which is supplied to the word line, even in the case where characteristics of the driving transistor of the word line have deteriorated.